soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions.
  在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现，或者快速搭建现场总线通信系统，实现灵活的CAN总线接口方案。
• I distinctly remember my high school self, wide-eyed, poring over the soft-core Starr report with friends.
  我还清楚地记得高中时代的我，睁大了眼睛，和朋友们一起狼吞虎咽地读着《斯塔尔报告》（StarrReport）中那些香艳的内容。
• Then, through the embedded soft-core processor technology based on FPGA, entire system the control, and processing and transmission of data of were achieved by using the co-design approach of hardware and software.
  然后，通过基于FPGA的嵌入式软核处理器技术，采用软硬件协同设计的方法，实现对整个系统功能的控制及数据的处理与发送。
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
• It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
  它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。
• First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
  先对灰度量化算法进行了分析和仿真比较，然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
• Implementation of Soft-Core Processor and DDFS Based on FPGA
  基于FPGA的软核处理器及DDFS实现
• SOPC includes soft-core or hard-core CPU 、 memory 、 I/ O and programmable logic resource, which has all the advantage of SOC 、 PLD and FPGA.
  SOPC综合了SOC、PLD和FPGA的优点，集成了硬核或软核CPU、存储器、I/O以及可编程逻辑。
• This paper introduces 8B/ 10B encoding technique, and puts forward a simple and practical realization method of an 8B/ 10B encoder. Furthermore, a versatile soft-core designed with Verilog is presented.
  本文介绍了8B/10B编码技术，提出了一种简单、实用的8B/10B编码器的实现方法，并且采用Verilog语言设计了一种通用的软核。
• With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
  通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。